Addressing memory exploits to enable Digital Security by Design
Here’s an excerpt from their chat:
Hello, welcome to this edition of Embedded Edge with Nitin. In this episode we take a look at computer system security architecture, especially some of the work being done by researchers over the last decade or so to address memory safety exploits through the CHERI project. CHERI stands for Capability Hardware Enhanced RISC Instructions. It comes from the work by SRI International and the University of Cambridge as well as companies like Arm, Microsoft and Google, to revisit fundamental design choices in hardware and software to dramatically improve system security. It has been supported by the DARPA CRASH, MRC, and SSITH programs since 2010, as well as other DARPA research and transition funding.
Since 2019, development of Arm’s experimental CHERI-enabled Morello processor, SoC, and board has been supported by the U.K. government’s research and innovation agency, UKRI. In January 2022, Arm announced a major milestone in this program, launching its Morello system on chip and demonstrator board. Morello prototype boards are now being released and are ready for software developers and security specialists to start using the Morello architecture to demonstrate enhanced security that can be achieved with hardware capabilities.
To learn more about the background to this, and the initiative led by the UKRI, we talk in this episode to John Goodacre, who leads UKRI’s Digital Security by Design, or DSbD, initiative. As DSbD’s Challenge Director, John is a veteran of the industry, and is professor of computer architectures at the University of Manchester. Before this, he was at Arm for almost 18 years, and among his achievements were the design and introduction of the ARM MPCore multicore processor and associated technologies that enabled today’s smartphone and became the foundation for future data centre infrastructure.
For the full recording and transcript visit EE Times. You can also find the recording on Apple Podcasts,
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