Delivered by Digital Catapult, funded by UKRI through the Digital Security by Design programme.
Documentation
Several key documents are available to get you started with Morello hardware and CheriBSD software, give you a detailed understanding of the CHERI architecture and Morello instruction set, and provide programming guidance. There are also several presentations to help you get started with CHERI & Morello concepts, and a number of academic papers.
Landing pages
Arm Morello Program
Document
Arm’s Morello developer resources, such as reference manuals and links to development tools (compilers, virtual platform)
Capability Hardware Enhanced RISC Instructions (CHERI)
Document
The University of Cambridge’s introduction to CHERI
University of Cambridge’s Morello resources
Document
University of Cambridge Morello resources
Manuals
Arm Morello System Development Platform (SDP) Preliminary Technical Reference Manual
Document
Hardware reference manual for the Morello SoC, including system features and register-level programming information.
Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 8)
Document
CHERI architecture specification
Arm Architecture Reference Manual Supplement – Morello for A-profile Architecture
Document
Morello instruction set reference manual
Presentations
DSbD YouTube channel
Document
Watch videos on the Digital Security by Design YouTube channel
DSbD | Microsoft – Manuel Costa
Document
Hardware memory safety challenges and opportunities
Enabling the Arm Morello Platform
Document
Details on Linaro’s firmware and system software enablement
Morello board unboxing video
Document
Watch Jeremey Singer from University of Glasgow unbox his Morello board
Blogs
Getting started with Morello Development Tools
Document
Getting started with Morello LLVM/Clang compilers, IDE, and the Fixed Virtual Platform
The Contribution of Digital Security in Cyber Security
Document
The Contribution of Digital Security in Cyber Security
Formal CHERI: rigorous engineering and design-time proof of full-scale architecture security properties
Document
How rigorous engineering methods were used to provide high assurance of key security properties of CHERI architectures
Papers
Technical Report – Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture
Document
This technical report describes CHERI ISAv8, the eighth version of the CHERI architecture being developed by SRI International and the University of Cambridge.
Technical Report – CHERI C/C++ Programming Guide
Document
This document is a brief introduction to the CHERI C/C++ programming languages.
CHERI Publications
Document
University of Cambridge publications and presentations on CHERI
An Introduction to CHERI
Document
CHERI concepts, software benefits, rules, and hardware implementation
Why you should care about CHERI
Document
Discussing CHERI as software compartmentalisation and as a fine-grained in-process memory safety mechanism.