Delivered by Digital Catapult, funded by UKRI through the Digital Security by Design programme.
Documentation
Several key documents are available to get you started with Morello hardware, give you a detailed understanding of the CHERI architecture and Morello instruction set, and provide programming guidance. There are also several presentations to help you get started with CHERI & Morello concepts, and a number of academic papers.
Landing pages
Capability Hardware Enhanced RISC Instructions (CHERI)
Landing pages
The University of Cambridge’s introduction to CHERI
Arm Morello Program
Landing pages
Arm’s Morello developer resources, such as reference manuals and links to development tools (compilers, virtual platform)
Manuals
Arm Morello System Development Platform (SDP) Preliminary Technical Reference Manual
Manuals
Hardware reference manual for the Morello SoC, including system features and register-level programming information.
Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 8)
Manuals
CHERI architecture specification
Arm Architecture Reference Manual Supplement – Morello for A-profile Architecture
Manuals
Morello instruction set reference manual
Presentations
DSbD | Microsoft – Manuel Costa
Presentations
Hardware memory safety challenges and opportunities
Enabling the Arm Morello Platform
Presentations
Details on Linaro’s firmware and system software enablement
Blogs
Papers
An Introduction to CHERI
Papers
CHERI concepts, software benefits, rules, and hardware implementation
Why you should care about CHERI
Papers
Discussing CHERI as software compartmentalisation and as a fine-grained in-process memory safety mechanism.